This invention relates to semiconductor circuit design for optical sensors and CCD sensor arrays. More specifically, the invention relates to a CCD device constructed with standard CMOS fabrication techniques and to a back illuminated imager that captures substantially all photoelectrons.
Various types of imagers (also sometimes referred to as image sensors) are in use today, including charge-coupled device (CCD) imagers and complementary metal-oxide semiconductor (CMOS) imagers. These devices are typically incorporated into CCD and CMOS imaging systems, respectively. Such imaging systems comprise an array of pixels, each of which contains a light-sensitive sensor element such as a CCD photogate or virtual photogate detector or, in CMOS imagers, a semiconductor substrate photodiode. Such light-sensitive sensor elements will be referred to herein, generally, as photodetectors.
The CCD photodetectors may be N-channel photogates that collect photoelectrons (i.e. electrons moved to a higher quantum state by interaction with photons) or P-channel photogates that collect photoholes (i.e. the positive charges left behind by the photoelectrons). As used herein, the term photocarriers refers generically to photoelectrons collected by an N-channel device or photoholes collected by a P-channel device.
CMOS imagers typically utilize an array of photodiodes as active pixel sensors and a row (register) of correlated double-sampling (CDS) circuits to sample and hold the output signal of a given row of pixel imagers of the array while removing the kTC noise component. Each active pixel typically contains a pixel amplifying device (usually a source follower transistor). The term active pixel sensor (APS) refers to electronic image sensors employing active devices, such as transistors, that are located within each pixel. CMOS imagers are often interchangeably referred to as CMOS APS imagers or as CMOS active pixel imagers. The active pixel sensors and accompanying circuitry for each pixel of the array will be referred to herein as APS circuits or APS pixel circuits.
In both CMOS and CCD imager systems, each photodetector accumulates charge and hence potential during the optical integration period in accordance with the light intensity reaching the relevant sensing area of the photodetector. As charge accumulates, the photodetector begins to “fill” or approach a saturation state. The charge stored in a photodetector is sometimes said to be stored in the “charge well” of CCD-type photodetectors located underneath an electrode overlying the semiconductor substrate. If the photodetector becomes full of charge or saturated prior to read-out, then excess charge is shunted off to a “blooming drain,” in part to prevent blooming. Blooming is a phenomenon in which excess charge beyond pixel saturation spills over into adjacent pixels, causing blurring and related image artifacts.
CMOS imagers have several advantages over CCD imagers such as reduced power consumption and miniaturization. CCD imagers typically use three different input voltages with separate, relatively high voltage power supplies to drive them. In addition, CCD arrays typically employ multiple overlapping gate electrodes in each pixel cell and the gates receive two or three respectively different clock phases. These gates are not feasible to form with standard CMOS processes. As can be appreciated, traditionally, it has not been easy to integrate CCD imagers with CMOS process peripheral circuitry due to complex fabrication requirements and relatively high cost of the specialized fabrication plant needed to produce such devices. By contrast, because CMOS imagers are formed with the same CMOS process technology as the peripheral circuitry used to operate the CMOS imager, such sensors are easier to integrate into a single system-on-chip using integrated circuit (IC) fabrication processes. By using CMOS imagers, it is possible to have monolithic integration of control logic and timing, image processing, and signal-processing circuitry such as analog-to-digital (A/D) conversion, all within a single sensor chip. Thus, CMOS cameras can be manufactured at low cost, relative to CCD cameras, because the imager, the peripheral circuitry and the signal processing circuitry all can be made using a standard CMOS IC fabrication processes.
In addition, CMOS devices use only a single power supply, which may also be used to drive peripheral circuitry. This gives CMOS imagers an advantage in terms of external circuitry complexity, and also in terms of the amount of chip area or “real-estate” devoted to power supplies. In this way, CMOS imagers have relatively low power requirements because of the relatively low voltage power supply required for operation, and also because only one row of pixels in the APS array needs to be active during readout.
Despite these advantages, however, CMOS imagers also have various disadvantages in comparison to CCD imagers. For example, CMOS optical sensor circuits are subject to reset noise, often referred to as “kTC noise.” reset noise is due to the on-resistance of the MOS transistor and is injected each time the transistor is reset. CMOS image sensors have two sources of reset noise: in the pixel and in the column processing circuitry. Reset noise is described in an article, entitled “Two-Phase Charge-Coupled Devices with Overlapping Polysilicon and Aluminum Gates” by W. F. Kosonocky and J. E. Carnes, in RCA Review, Vol. 34, March 1973, pp. 164-203. Reset noise is considered to be a type of thermal noise. The kTC noise magnitude is related to k, the Boltzmann constant, T, the temperature in Kelvin, and C, the capacitance in the current path. Technically, the magnitude of the noise is proportional to the square root of the product of the Boltzmann constant, the temperature in Kelvin, and the capacitance in the pixel's current path. The local temperature variations in each pixel give rise to this random noise. Immediately after the reset operation, the pixel may have a non-zero signal value, equal to the kTC noise. Many CMOS imagers employ correlated double sampling (CDS) circuits to cancel this noise from the imager output. CDS circuits operate by sampling the noise value immediately after reset and subtracting the noise from the pixel value at the end of the integration period. CCD imagers may be reset without significant noise by simply transferring any charge in the imager cell to a charge dump using the normal CCD charge transfer techniques. Because it may occur on a pixel-by-pixel basis, some imager arrays need a frame store memory to effectively reduce reset noise.
It would be desirable to provide an image sensor which addresses known disadvantages of CMOS imagers, by employing CCD imaging technology in a single semiconductor device manufactured using a standard CMOS fabrication process.